Chip multiprocessors (CMPs) will become mainstream by the end of the decade. Contemporary CMPs are built using a “copy-exactly” approach. In CMPs built using the copy-exactly approach, all central processing units (CPU) on a CMP are identical, having exact copies of ALUs, caches and pipelines. This approach minimizes the design complexity of CMPs, since only one CPU needs to be designed, but is instantiated multiple times.
Some software applications are sensitive to single thread performance, and others are sensitive to multi-thread or throughput performance. For those applications that are sensitive to single thread performance, and can benefit from more resources, it is desirable to allocate more resources to the CPU running the single thread, and less to those CPUs that are running less performance sensitive threads. For those applications that are sensitive to multi-thread performance, it is beneficial to share resources more uniformly amongst all threads. Additionally, applications may themselves vary, sometimes being more performance sensitive to a single thread, and other times to all threads.
CMPs in development also must deal with a limit on power dissipation and current draw. For example, if all CPUs are fully active simultaneously, voltage and frequency must be lowered to ensure that the CMP stays below the current and power limits. However, if a single CPU is active, the voltage and frequency can be set to the maximum voltage and frequency and all available resources allocated thereto. If power and current is allocated per-CPU, the CPUs allocated more power could run programs faster relative to other CPUs that are allotted less. With added intelligence (either directives by software, or inferences by software or hardware algorithms), a CMP could allocate power to improve the performance of one or more particular threads of execution, or balance power to maximize throughput of all threads. Thus chip power becomes a resource to be allocated.